august 2011 ?2011 fairchild semiconductor corporation FDMC8030 rev.c www.fairchildsemi.com 1 FDMC8030 dual n-channel power trench ? mosfet FDMC8030 dual n-channel power trench ? mosfet 40 v, 12 a, 10 m features ? max r ds(on) = 10 m at v gs = 10 v, i d = 12 a ? max r ds(on) = 14 m at v gs = 4.5 v, i d = 10 a ? max r ds(on) = 28 m at v gs = 3.2 v, i d = 4 a ? termination is lead-free and rohs compliant general description this device includes two 40v n-channel mosfets in a dual power 33 (3 mm x 3 mm mlp) package. the package is enhanced for exceptional thermal performance. applications ? battery protection ? load switching ? point of load mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 40 v v gs gate to source voltage (note 4) 12 v i d drain current -continuous t a = 25 c (note 1a) 12 a -pulsed 50 e as single pulse avalanche energy (note 3) 21 mj p d power dissipation t a = 25 c (note 1a) 1.9 w power dissipation t a = 25 c (note 1b) 0.8 t j , t stg operating and storage junction temperature range -55 to +150 c r ja thermal resistance, junction to ambient (note 1a) 65 c/w r ja thermal resistance, junction to ambient (note 1b) 155 device marking device package reel size tape width quantity FDMC8030 FDMC8030 power 33 13 ?? 12 mm 3000 units d1 d2 s1 g1 s2 g2 power 33 pin 1 s1 s1 s2 s2 g2 s2 g1 s1 s2 s2 s1 s1 4 3 2 1 8 7 6 5 bottom drain1 contact bottom drain2 contact q2 q1
FDMC8030 dual n-channel power trench ? mosfet www.fairchildsemi.com 2 ?2011 fairchild semiconductor corporation FDMC8030 rev.c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v 40 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 19 mv/c i dss zero gate voltage drain current v ds = 32 v, v gs = 0 v 1 a i gss gate to source leakage current, forward v gs = 12 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 1.0 1.5 2.8 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -5 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 12 a 8 10 m v gs = 4.5 v, i d = 10 a 10 14 v gs = 3.2 v, i d = 4 a 19 28 v gs = 10 v, i d = 12 a t j = 125 c 13 16 g fs forward transconductance v dd = 5 v, i d = 12 a 57 s c iss input capacitance v ds = 20 v, v gs = 0 v f = 1mhz 1462 1975 pf c oss output capacitance 321 430 pf c rss reverse transfer capacitance 20 30 pf r g gate resistance 0.9 2.5 t d(on) turn-on delay time v dd = 20 v, i d = 12 a v gs = 10 v, r gen = 6 713ns t r rise time 310ns t d(off) turn-off delay time 19 33 ns t f fall time 310ns q g(tot) total gate charge v gs = 0 v to 10 v v dd = 20 v i d = 12 a 21 30 nc total gate charge v gs = 0 v to 5 v 12 17 nc q gs gate to source charge 2.8 nc q gd gate to drain ?miller? charge 2.5 nc v sd source to drain diode forward voltage v gs = 0 v, i s = 12 a (note 2) 0.83 1.2 v t rr reverse recovery time i f = 12 a, di/dt = 100 a/ s 25 40 ns q rr reverse recovery charge 9 18 nc notes: 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0 %. 3. e as of 21 mj is based on starting t j = 25 o c, l = 0.3 mh, i as = 12 a, v dd = 36 v, v gs = 10 v. 100% tested at l = 3 mh, i as = 5 a. 4. as an n-ch device, the negative v gs rating is for low duty cycle pulse occurenc e only. no continuous rating is implied. a. 65 c/w when mounted on a 1 i n 2 pad of 2 oz copper b.155 c/w when mounted on a minimum pad of 2 oz copper
FDMC8030 dual n-channel power trench ? mosfet www.fairchildsemi.com 3 ?2011 fairchild semiconductor corporation FDMC8030 rev.c typical characteristics t j = 25c unless otherwise noted figure 1. 012345 0 10 20 30 40 50 v gs = 3 v v gs = 10 v v gs = 3.5 v pulse duration = 80 p s duty cycle = 0.5%max v gs = 4.5 v v gs = 3.2 v i d , drain current (a) v ds , drain to source voltage (v) on-region characteristics figure 2. 0 1020304050 0 1 2 3 4 5 v gs = 10 v pulse duration = 80 p s duty cycle = 0.5%max normalized drain to source on-resistance i d , drain current(a) v gs = 3.5 v v gs =3.2 v v gs = 3 v v gs = 4.5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n - r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 i d = 12 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 24681 0 0 5 10 15 20 25 30 i d = 12 a t j = 25 o c t j = 125 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5%max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 1234 0 10 20 30 40 50 t j = 25 o c t j = -55 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5%max t j = 150 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 50 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMC8030 dual n-channel power trench ? mosfet www.fairchildsemi.com 4 ?2011 fairchild semiconductor corporation FDMC8030 rev.c figure 7. 0 5 10 15 20 0 2 4 6 8 10 i d = 12 a v dd = 15 v v dd = 20 v v gs , gate to source voltage(v) q g , gate charge(nc) v dd = 25 v gate charge characteristics figure 8. 0.1 1 10 40 1 10 100 1000 2000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.001 0.01 0.1 1 10 20 1 10 30 t j = 100 o c t j = 25 o c t j = 125 o c t av , time in avalanche(ms) i as , avalanche current(a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 0.01 0.1 1 10 100200 0.01 0.1 1 10 60 100 p s 10 ms 10 s 100 ms dc 1 s 1 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 155 o c/w t a = 25 o c f orw ard bi as safe operating area figure 11. single pulse maximum power dissipation 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.1 1 10 100 1000 p (pk) , peak transient power (w) single pulse r t ja = 155 o c/w t a = 25 o c t, pulse width (sec) typical characteristics t j = 25c unless otherwise noted
FDMC8030 dual n-channel power trench ? mosfet www.fairchildsemi.com 5 ?2011 fairchild semiconductor corporation FDMC8030 rev.c figure 12. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.001 0.01 0.1 1 single pulse r t ja = 155 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 2 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25c unless otherwise noted
FDMC8030 dual n-channel power trench ? mosfet www.fairchildsemi.com 6 ?2011 fairchild semiconductor corporation FDMC8030 rev.c dimensional outline and pad layout
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